Integra™ Products

The Integra™ products from Virage Logic offer an integrated approach to a high performance, scalable, low power, physical design aware SoC Infrastructure. The Integra™ portfolio provides more than just the interconnect IP; it is a complete solution with IP for efficient data and control interconnect networks, complemented with patented techniques for Quality of Service (QoS), power management and controllers for embedded memory.

Integra™ ON-Chip Communication Networks

Virage Logic IntegraTM portfolio offers a full range of On-chip Communication Networking Solutions, for many applications including Microcontrollers, In-Car Entertainment, Digital TV, Set Top Box and Networking.

• Multi-Layer Network
  The Integra ML Network is a proven interconnect technology that addresses the needs of a broad range of SoCs. It is a scalable interconnect that supports the construction of a great variety of networks from a set of basic components like switches (multi-layer buses), bridges, adaptors, etc. This allows it to provide area-efficient interconnect solutions for low-end SoCs that require just a single bus in a single power and clock domain as well as for high-end SoCs that require more extensive interconnect structures with multiple power and clock domains.

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• Control Network
  The Integra Control Network has been developed to provide an efficient way to connect dozens or even hundreds of control targets while optimizing power consumption, area and wire count. By allowing the connections to be made over long distances, and allowing each initiator or target to operate at a different frequency, the Integra Control Network allows the SoC architect to concentrate on the IP blocks, not worrying about the interconnect. Furthermore, because each connected device can be independently powered off without impacting the rest of the Integra Control Network, IP blocks do not need to remain powered when not in use.

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• QoS Engine
  SoC development typically includes the integration of a number of system functions that have real-time constraints, for which performance guarantees must be provided. Examples are a video display engine with an input buffer that is not allowed to run empty, or audio processing on a CPU that can sustain only so much latency for its memory accesses in order to meet its deadlines. Traditionally, correct integration of such key functions is time-consuming and often implies additional cost because of over-dimensioning (e.g. by requiring additional memory bandwidth).The QoS Engine addresses these SoC integration issues by providing Quality of Service (QoS) guarantees to on-chip cores that request access to off-chip DRAM.

More details are available here