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SiANA™ ANALOG IP SOLUTIONS 90NM – 65NM – 40NM
Virage Logic’s Analog Solutions SiANA™ product line is silicon proven, area effective, high performance, and is low power optimized for advanced process nodes from 90nm to 40nm. All SiANA products are rigorously verified and characterized to help reduce risk, improve time-to-market, and maximize yield. Virage Logic’s state-of-the-art design for test support allows for a smooth transition into mass production testing. SiANA™ Product Portfolio - Clock Sources
The SiANA Clock Sources products deliver small area and high performance clock generators (oscillators) and multipliers (PLL). For the multi-purpose PLLs, both a Fractional-N and a Spread Spectrum option are available. - Data Converters
The SiANA Data Converter products provide small area and high performance for a wide range of applications like control, audio, video and IF interfaces. - Sensors
The SiANA Sensor products are specially designed to measure data for SoC and ASIC designs that allow the same system to take measures e.g. clock frequency scaling or power management. Analog Front-Ends Based on the SiANA product portfolio, application knowledge and chip integration capabilities, Analog Front-Ends provide integrated full function GDSII in the next application domains: - Audio
- Up to and including CD quality
- Video
- I/O supporting RGB, Component, S-video and Composite
- IF interfaces
- Single and dual antennas optimized solutions
- MIMO solutions (3+ antennas)
Technology Selector for SiANA Component IP Deliverables | Class | View | INITIAL
Package | FINAL
Package | | Abstract | LEF | ● | ● | | Behavior | Verilog behavioral model | ● | ● | | Documents | Brief | ● | ● | | Datasheet | ● | ● | | Silicon report | | ● | | Release notes | ● | ● | | Interface | VHDL entity & package | ● | ● | | Verilog interface | ● | ● | | Layout | GDSII | | ● | | Netlist | CDL | | ● | | Test | CTL scan chains control file | ● | ● | | TD scan chains control file | ● | ● | | Verilog netlist after scan insertion | ● | ● | | ATPG fastscan control file | ● | ● | | Test bench | Verilog test bench | ● | ● | | Timing | LIB for each relevant PVT corner | ● | ● | | Scripts | Run scripts for nccoex | ● | ● | For more information on SiANATM, contact: SiANA@viragelogic.com
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