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2009 Articles
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October 15, 2009
Implementing an all-digital PHY and delay-locked loop for high-speed DDR2/3 memory interfaces
By Luigi Ternullo, Virage Logic
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October 13, 2009
Virage absorbs a key piece of NXP: signs for the future of IP?
By EDN
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September 29, 2009
Ensuring data security in logic non-volatile memory applications: Floating-gate versus oxide rupture
By Todd Humes
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July 1, 2009
Design trust and verification
By Nicolas Mokhoff, EDA DesignLine
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July 1, 2009
First Down On The 40nm Line
By Low-Power Design
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June 30, 2009
Auto Industry Replaces Fuse Technology with Standard CMOS Based MTP; Adds Functionality, Testability and Reliability
by Craig Zajac
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June 29, 2009
Should Dual Rail Go Mainstream in Deep Nanometer Era?
by Vipin Tiwari
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EETImes
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June 25, 2009
Exec: Memory business model is broken
By Mark LaPedus
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EETImes
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June 25, 2009
Memory interface IP sector heats up
By Mark LaPedus
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June 25, 2009
Tool Automates Power Optimization Of Embedded SoC Memories
by David Maliniak
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EETImes
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June 24, 2009
Aeon memory technology gets automotive qualification
by Christoph Hammerschmidt, EE Times Europe
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June 24, 2009
Non-Volatile Memory Qualified For Rigorous Automotive Standard
by ED News Staff
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June, 2009
IP Metrics Article: Selecting IP in a Complex Design Environment
By Raghavan Menon, VP of Engineering, ASIP Solutions, Virage Logic
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May 27, 2009
Maximizing a Low-Power Memory Interface IP Subsystem
By Luigi Ternullo
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May 20, 2009
Virage Logic claims first 65-nm multi-time programmable logic non-volatile memory IP
By Embedded
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May 20, 2009
Virage Logic Introduces Multi-Time Programmable 65-nm Non-Volatile Memory
By EDN
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April 2009
Experts At The Table: Greener Design
Part #1 | Part #2 | Part #3
By Ed Sperling
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EETImes
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February 9, 2009
Analysis: Plug-and-play IP goal remains elusive
by Dylan McGrath, EE Times
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