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Intelli™ DDR2/3 PHY + DLL + I/O
The Intelli DDR 2/3 PHY + DLL is an all-digital PHY + DLL solution providing the high-performance and resolution required to meet 1.6 Gb/s data rates for DDR3 interface solutions. The all-digital PHY + DLL solution provides maximum portability to different technologies and consumes lower power and smaller area as compared to traditional analog solutions.
As part of the Intelli DDR2/3 System Aware IP™ Memory Interface Solution, the Intelli DDR2/3 PHY + DLL includes system level knowledge to deliver automated capabilities that can signal potential variations in silicon, package and/or board design and manufacturing.
- Low Power
- All-digital solution consumes less power than analog solution
- Delay line controlled with intelligent clock gating
- Intelligent management of outputs to minimize I/O switching
- High Performance
- Automatic PVT compensation to ensure proper alignment of DQS at all performances
- Read and Write leveling provides fine tuning of data capture and launch to support high performance operations
- Noise immunity circuitry to filter clock jitter
- Small Area
- All-digital solution consumes less area than analog solutions
Intelli™ DDR2/3 I/O
Intelli DDR2/3 I/Os are architected in conjunction with the capabilities of the Intelli DDR2/3 PHY+DLL to further maximize system level performance and minimize power. The affects on signal quality that can occur due to package board level design and manufacturing variability can dramatically affect the functionality and performance of a high speed DDR interface in the system environment. The Intelli DDR3 I/Os are a critical component in the DDR3 interface solution and are architected to provide additional capabilities above and beyond the JEDEC standard to maximize system level success. Several capabilities have been developed in the Intelli DDR2/3 IO to help manage performance and power for potential system level variations.
- Low Power
- Techniques to minimize crow bar current
- Several drive strengths to optimize performance and power
- DC path shut down
- High Performance
- Slew rate control to optimize system level edge rates
- Driver pre-emphasis to optimize signal quality
- Duty cycle control to balance DQ sample window
- Highly configurable I/Os to meet the needs of most system environments
- Complete DDR I/O Package
- I/O cell, clock driver cell, control driver cells, breaker cells, etc.
Luigi Ternullo, Virage Logic Intelli™ DDR Product Marketing Manager
DDR All-Digital PHY+DLL Video Overview
Addressing DDR System Level Concerns Video Overview
DDR High Speed Interfaces for Increasing Performance and Reducing Power Video Overview
DDR High-Speed Interface Solutions
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