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Intelli™ PHY+DLL
Virage Logic’s Intelli PHY+DLL is a flexible and advanced solution for DRAM Physical Layer Interfaces (PHY) for ASIC and SoC designers requiring high-performance from a memory interface using the least amount of area. The Intelli PHY+DLL supports standard SDRAM, and DDR SDRAM, as well as a wide variety of standards for each type, including single data rate JEDEC standard SDRAM and Mobile SDRAM, double data rate JEDEC standard DDR1/2, DDR2/3, DDR3, MobileSDR, MobileDDR, SDR, and GDDR DRAM. The PHY is designed for easy integration, and includes features such as DQS squelch.
The DLL portion of the solution is an all digital design for easy integration, test, support, and migration to new process technologies. The digital solution also provides lower power, smaller die size, and superior control for temperature and supply variations, with reduced noise immunity for very low jitter operations.
Benefits of Intelli PHY+DLL:
- Maximum portability with digital implementation
- PHY+DLL to support 1.6 Gbs
- Leverages silicon proven standard cell library technology
- Easily ports to multiple foundries for a variety of process nodes
Multi-protocol Solution:
- Smallest area with superior performance
- Combines all required protocols in a single solution – for multiple designs
- System price vs. performance tradeoffs for multiple DRAM protocols
Luigi Ternullo, Virage Logic Intelli™ DDR Product Marketing Manager
DDR All-Digital PHY+DLL Video Overview
Addressing DDR System Level Concerns Video Overview
DDR High Speed Interfaces for Increasing Performance and Reducing Power Video Overview
DDR High-Speed Interface Solutions
Virage Logic demo of the 1.6 Gb/s Intelli(tm) DDR3 memory system, running on a SoC using the Intelli DDR2/3 Controller & Intelli DDR2/3 PHY+DLL & I/O
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