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Interface IP Solutions
Virage Logic’s Interface IP Solutions are designed to meet the highest quality and performance standards for functional IP and contains application-specific functional IP targeted to a variety of market requirements for high-performance, low-power, low-gate count, and small die size.
This product line includes an entire system solution for the full breadth of memory interface designs, from the semiconductor industry’s trusted IP partner, to help accelerate silicon success. System solution needs are addressed with the Intelli™ DDR System Aware IP™ Memory Interface Solution. Virage Logic’s System Aware IP provides system level knowledge that is incorporated in the IP components to help achieve lowered system costs, reduce risk and meet the time-to-market window associated with the complete system. System Aware IP merges both IP design expertise and system level design expertise to develop a solution that is robust, yet flexible enough to account for potential system level variations without impacting the area, power, or performance of the IP.
Virage Logic’s Intelli DDR System Aware IP is comprised of a highly optimized memory controller, all-digital PHY + DLL and I/O. Each of the IP components is architected to address potential signal integrity issues that can be related to variations in silicon, package and/or board design and manufacturing. These potential variations can adversely affect the in-system operation of the DDR memory interface, but the Intelli DDR System Aware IP solution is architected to address these issues through automatic calibration and/or through user controlled configurations.
Virage Logic’s System Aware IP Solution includes the Intelli DDR3 memory controller, digital PHY + DLL and I/O.
Benefits of Virage Logic’s Interface IP Solutions
These products are commonly based on Virage Logic's proprietary and patented logic libraries, routing methodology, and cell architecture.
- Developed using a robust advanced verification methodology
- Overall reduction in development schedule and costs
- Improved time-to-market
- Reduced risk
Virage Logic’s Intelli DDR memory controller interface solution includes a memory controller and the related PHY and DLL, with advanced features to deliver high-performance in a minimum die area with low power dissipation. The Intelli DDR solution is implemented for several SDR and DDR protocols, including MobileSDR, MobileDDR, and GDDR DRAM, as well as DDR1, DDR2, and DDR3 for several foundries on a variety of processes nodes.
Intelli™ Controller
The Intelli DDR controller is architected to achieve the highest data throughput efficiency while maintaining a small gate count. The benefit of a high efficiency controller solution translates to the highest performance for any clock frequency or the lowest power for any given data throughput.
Intelli™ DDR2/3 PHY+DLL+I/O
The Intelli DDR 2/3 PHY+DLL+I/O combines the all-digital PHY+DLL and advanced DDR2/3 I/O providing the high-performance and resolution required to meet 1.6 Gb/s data rates for DDR3 interface solutions. The combination of these highly optimized IP components delivers a high performance system solution by addressing potential system level signal integrity concerns through automatic and user controlled configurable features. It is only by architecting this solution in the context of the compete system that it is possible to address potential system level concerns.
Intelli™ PHY+DLL
Virage Logic’s Intelli PHY+DLL is an all digital, high-performance, low-power, and silicon efficient implementation of the physical interface required for a memory interface solution. The Intelli PHY+DLL works seamlessly with all of the Intelli DDR memory controllers to simplify design, ease integration, and lower risk.
Intelli™ Models
The Virage Logic Intelli Models include advanced features to reduce simulation time, improve test coverage, speed time-to-market, and reduce system design risk. Memory models work within the design of a memory system to quickly and accurately model all memory device features and timing parameters for easy testing of a completed system.
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