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2008 Articles
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December 2, 2008
Non-Volatile Memory Options in Portable Designs
by Craig Zajac, Virage Logic
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November 13, 2008
DDR3 Memories Aim at SoC Designs
By Luigi Ternullo, Virage Logic Corp.
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October 16, 2008
DDR3 Memory targets SoC Designs
By Luigi Ternullo, Virage Logic Corp.
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September 24, 2008
Memory Design Considerations When Migrating to DDR3 Interfaces from DDR2
by Virage Logic
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September 8, 2008
Comparing an IP-Centric DDR Solution with a System-Centric DDR Solution for Improved System Performance
by Virage Logic
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September 9, 2008
Analog Devices licenses Aeon non-volatile memory
by Peter clarke, EE Times
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August 29, 2008
CEO Interview: Dan McCranie, Virage Logic
by Portable Design News
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July 16, 2008
Improving Yield Requires Retooling and a Robust Data Exchange Infrastructure
by TapeOut Magazine
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July 16, 2008
Virage extends DDR3 offering
by Nicolas Mokhoff, EE Times
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July 14, 2008
1.6 Gb/s DDR3 Solution For 65 nm SoCs
by Portable Design News
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July 14, 2008
Virage Logic pushes into DDR3 territory with full interface IP
By EDN Executive Editor Ron Wilson
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June 16, 2008
From system-level design to hardware prototypes
by Test & Measurement World
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June 30, 2008
Virage Logic pays $5.2M for Impinj non-volatile memory IP business
By Suzanne Deffree, Managing Editor, News -- Electronic News
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June 30, 2008
Virage buys Impinj's memory IP business
by Mark LaPedus, EE Times
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June 18, 2008
Virage rolls memory IP for code storage
by Mark LaPedus, EE Times
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June 10, 2008
Video: Virage's McCranie says IP is alive and well
by EE Times
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June 5, 2008
Virage Logic Delivers Open RTL-to-Test-Floor Embedded Memory Test and Repair Subsystem
by Portable Design News
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May 30, 2008
Virage rolls DRAM physical layer interface IP
by Mark LaPedus, EE Times
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May 8, 2008
CSR selects Virage memory IP for wireless ICs
by Test & Measurement World
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May 6, 2008
Virtualization Company 3Leaf to Use Virage Logic's Memory Controller
by Virtualization News Desk
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April 30, 2008
Virage Logic Reports Second Quarter Fiscal Year 2008 Results
by Forbes.com
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April 30, 2008
Make an Informed Build or Buy Decision for Memory-Controller Solutions
by Raj Mahajan and Raghavan Menon, Virage Logic
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April 30, 2008
CSR Selects Virage Logic as IP Partner for Bluetooth
by Chip Design
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April 22, 2008
Virage Logic Intelli DDR Memory Controller Interface Improves Efficiency
by EDA Geek
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April 17, 2008
Virage Logic adds 65-nm Common Power Format low-power standard cell libraries to portfolio
By Ann Steffora Mutschler, Senior Editor -- Electronic News
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April 17, 2008
Virage Logic Strengthens Low Power IP Product Portfolio with Availability of 65nm CPF-Enabled Ultra-Low-Power Standard Cell Libraries
by Industry News
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April 17, 2008
Virage Logic Strengthens Low Power IP Product Portfolio with Availability of 65nm CPF-Enabled Ultra-Low-Power Standard Cell Libraries
by Business Wire
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April 8, 2008
Virage Logic Compiler and IP Fits TSMC 40nm Process
by Chip Design
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April 7, 2008
Virage Logic First to Deliver Complete Memory Compiler and Logic Library IP Portfolio for TSMC 40nm Process
by Analog & DSP News
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April 8, 2008
Virage Logic Delivers Memory Compiler And Logic Library For TSMC 40nm Process
by Semiconductor online
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April 7, 2008
Memory Compiler and Logic Library IP Portfolio for TSMC 40nm Process
by Portable Design News
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April 7, 2008
The infrastructure buildout begins with libraries for the 45 nm node
by EDN Executive Editor Ron Wilson
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March 2008
Improving Yield With Retooling and Robust Infrastructure
by Yervant Zorian, Ph.D.; Gevorg Torjyan, Ph.D.; and Dan Nenni, Virage Logic
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March 11, 2008
'We Want to Expand Business in Japan and Asia,' CEO of IP Core Vendor Virage Logic Speaks
By Tech-On! - LSI Information
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February 20, 2008
Critical Design & Manufacturing Challenges at 45 nm
By Brani Buric, Virage Logic
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February 2008
Margin Myopia Blurs Chip Supply Chain Future
By John Blyler
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February 13, 2008
How to select a DDR memory controller
By Raj Mahajan and Raghavan Menon, Virage Logic
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