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SiWare™ Logic for 40nm & 65nm
The SiWare Logic product line includes yield-optimized, design for manufacturability (DFM) compliant standard cells for a wide variety of design applications at the advanced nodes. SiWare Logic libraries are offered using three separate architectures to optimize circuits for High-Density, Ultra-High-Density or High-Speed for area, speed, and power tradeoffs.
Key Features
- DFM compliant for high yield
- Poly M2 alignment for restricted design rules (RDR)
- Standard, High and Low thresholds for power/performance tradeoffs
- Low voltage corners for dynamic power saving
- Temperature inversion corners for timing accuracy
- Industry standard EDA flow support (CCS, ECSM)
- Ultra low power kit
- Engineering Change Order (ECO) Kit
Performance vs. Area for High-Density, High-Speed and Ultra-High-Density Libraries
Ultra-low-power (ULP) extension libraries help designers minimize power consumption while sustaining optimal performance for applications that demand the absolute minimal power consumption. ULP library kits enable designers to dynamically operate functional blocks at multiple voltages to achieve optimal tradeoffs between dynamic power consumption and performance in multiple operating modes with:
- Level shifters for multiple voltage islands
- Power-gating for domain isolation
- Data retention flip-flops and always-on cells for fast wake-up
- Biasing cells for leakage control
- Pitch matched to High-Density, High-Speed and Ultra-High-Density cells
- Available in multiple thresholds
- Support for industry-standard EDA power flows
The ECO extension library kits provide designers the flexibility to create logic elements using metal only for cost effective bug fixing. Designers can use these kits after a chip has been placed and routed to accommodate last minute product requirements or correct final verification issues with:
- Base array filler cells
- Metal programmable macros
- Combinational, sequential, and support cells
- Multiple drive strengths
- Characterized for 7 corners including temperature inversion
Product Video
Ken Brock, Virage Logic Director Physical IP Marketing
Standard Cell Logic Libraries for Demanding Speed Requirements Video Overview
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