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SiWare™ Logic for 65nm - 40nm - 28nm
The SiWare Logic product line includes yield-optimized, design for manufacturability (DFM) compliant standard cells for a wide variety of design applications at the advanced nodes. SiWare Logic libraries are offered using three separate architectures to optimize circuits for High-Density, Ultra-High-Density or High-Speed for area, speed, and power tradeoffs.
Ideal for customers in the graphics, networking, storage, cell phone, and other high performance applications requiring high density and low power, Virage Logic's SiWare 65nm, 40nm and 28nm technologies provides a dashboard of options to enable reduced die size, optimal power management, high performance and test and repair options. This capability enables customers to differentiate their products with respect to speed, area, dynamic power, standby power, and cost.
Key Features
- DFM compliant for high yield
- Poly M2 alignment with restricted design rules (RDR) minimum area
- Standard, High and Low thresholds for power/performance tradeoffs
- Low voltage corners for dynamic power saving
- Temperature inversion corners for timing accuracy
- Industry standard EDA flow support (CCS, ECSM)
- Power Optimization Kit
- Engineering Change Order (ECO) Kit
Performance vs. Area for High-Density, High-Speed and Ultra-High-Density Libraries
Power Optimization Kits enable designers minimize power consumption while sustaining optimal performance for applications that demand the absolute minimal power consumption. Power Optimization Kits enable designers to dynamically operate functional blocks at multiple voltages to achieve optimal tradeoffs between dynamic power consumption and performance in multiple operating modes with:
- Level shifters for multiple voltage islands
- Power-gating for domain isolation
- Data retention flip-flops and always-on cells for fast wake-up
- Biasing cells for leakage control
- Pitch matched to High-Density, High-Speed and Ultra-High-Density cells
- Available in multiple thresholds
- Support for industry-standard EDA power flows
The ECO extension library kits provide designers the flexibility to create logic elements using metal only for cost effective bug fixing. Designers can use these kits after a chip has been placed and routed to accommodate last minute product requirements or correct final verification issues with:
- Base array filler cells
- Metal programmable macros
- Combinational, sequential, and support cells
- Multiple drive strengths
- Empty sites can be filled with DCAP cells
Additional Resources 40nm
Additional Resources 65nm
Additional Resources 28nm
Product Video
Ken Brock, Virage Logic Director Physical IP Marketing
Standard Cell Logic Libraries for Demanding Speed Requirements Video Overview
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