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SiWare™ Memory 65nm - 40nm -28nm
The SiWare Memory product line provides a powerful dashboard that enables SoC designers to explore the tradeoffs between performance, area, power and statistical yield to generate optimal memory configurations. This “dashboard control” capability is key at 65nm and critical at 40nm where design and process complexities require sophisticated management of the various tradeoffs in order to effectively meet stringent end-product requirements and increasingly narrow market windows.
Virage Logic’s full suite of 28nm SiWare Memory compilers provide an ideal solution for customers in the graphics, networking, storage, cell phone, and other high performance applications requiring high density and low power. SiWare Memory enables low risk 28nm designs for early industry adopters.
- Performance vs. Area
Select between High-Density vs. High-Speed SRAM compilers for 30-70% performance improvement
- Performance vs. Leakage power
Power Saver mode saves 60% of static power as compared to Performance mode
Process threshold variants provide option to trade off performance vs. leakage
- Area vs. Dynamic power
Multiple bank options in SRAM compilers to trade-off area for up to 55% lower dynamic power.
- Performance vs. Dynamic power
DVFS supported by ultra low voltage operation characterization at 20% below nominal voltage for 40% dynamic power reduction
- Performance vs. Yield
Read/Write Margin settings and Sigma-based design characterization to manage local process variance based on memory size and number of memories per chip
- Area vs. Yield
SRAM compilers have option to use column redundancy to trade-off area for yield. Customers have reported 50%-250% better yield due to repairable memories.
- Testability Choices
Options for external, integrated at-speed test and redundancy
Supported by STAR Memory System for test and repair
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28nm Memory Compilers
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Node
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Variant
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High Density Single Port SRAM
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28HPL
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SVt with LVt Periphery Option
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High Density Dual Port SRAM
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28HPL
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SVt with LVt Periphery Option
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High Density 1-Port Register File
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28HPL
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SVt with LVt Periphery Option
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High Density 2-Port Register File
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28HPL
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SVt with LVt Periphery Option
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VIA12 ROM
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28HPL
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SVt with LVt Periphery Option
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High Speed 1-Port Register File Cache
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28HPL
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SVt with LVt Periphery Option
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High Density Single Port SRAM
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28HP
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SVt Array/ Mixed Vt Periphery
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High Density Dual Port SRAM
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28HP
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SVt Array/ Mixed Vt Periphery
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High Density 1-Port Register File
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28HP
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SVt Array/ Mixed Vt Periphery
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High Density 2-Port Register File
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28HP
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SVt Array/ Mixed Vt Periphery
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Ultra High Density 2-Port Register File
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28HP
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SVt Array/ Mixed Vt Periphery
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VIA12 ROM
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28HP
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SVt Array/ Mixed Vt Periphery
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STAR 16M Single Port SRAM
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28HP
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SVt Array/ Mixed Vt Periphery
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High Speed Single Port SRAM
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28HP
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SVt Array/Mixed Vt Periphery
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High Speed Dual Port SRAM
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28HP
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SVt Array/Mixed Vt Periphery
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| 40nm Memory Compilers |
Maximum Size
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Aspect ratios
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Bank options
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Bit-write
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Read pipeline
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Single-port High Density SRAM
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1280k bits
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3
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1, 2, 4
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Yes
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Yes
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Single-port High Speed SRAM
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1280k bits
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3
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1, 2, 4
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Yes
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Yes
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Dual-port High Density SRAM
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1280k bits
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3
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1, 2, 4
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Yes
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Yes
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Dual-port High Speed SRAM
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1280k bits
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3
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1, 2, 4
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Yes
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Yes
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Single-port Register File
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64k bits
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2
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1, 2
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Yes
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Yes
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Two-port Register File
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64k bits
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3
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1, 2
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Yes
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Yes
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Ultra-High-Density Two Port
Register File
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64k bits
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2
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1, 2
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Yes
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Yes
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Two-Port High-Speed Asynchronous
Register File
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64k bits
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3
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1
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Yes
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No
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Ultra-High Capacity 8 Megabit SRAM
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8Mbits
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4
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1,2,4,8
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N/A
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Yes
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Via12 ROM
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1280k bits
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4
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1,2,4,8
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No
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No
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| 65nm Memory Compilers |
Maximum Size
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Aspect ratios
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Bank options
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Bit-write
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Read pipeline
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Single-port High Density SRAM
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640k bits
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3
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1, 2, 4
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Yes
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Yes
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Single-port High Speed SRAM
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1280k bits
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3
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1
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Yes
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Yes
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Dual-port High Density SRAM
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640k bits
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3
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1, 2, 4
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Yes
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Yes
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Single-port Register File
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64k bits
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2
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1
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Yes
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No
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Two-port Register File
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64k bits
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3
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1
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Yes
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No
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Via23 ROM
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1280k bits
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3
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1
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No
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No
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Metal1 Contact/Via12 ROM
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6144k bits
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3
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1
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No
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No
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- SiWare memories provide the broadest EDA view support for commercially available embedded memories to integrate easily into flows from leading EDA companies such as Cadence, Magma, Mentor & Synopsys.
- Power mesh support to ensure robust power distribution inside memories
- Seven operating PVTs supported including voltage inversion corners & ultra low voltage corners
Lisa Minwell, Virage Logic Technical Marketing Director
Highly Configurable Memory for Advanced Power Management Video Overview
Existing Customers
New Customers
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