Accelerating Silicon Success with Silicon Aware IP™

Long known as the technology leader in semiconductor Physical IP (intellectual property), particularly for 130-nanometer (nm) and below processes, Virage Logic continues to demonstrate its superior technology vision with its Silicon Aware IP™ initiative. Silicon Aware IP is Physical IP, such as memories, logic and I/Os, designed with embedded Infrastructure IP for test, diagnostics, repair, and yield enhancements. The result is IP that is high yielding and enables rapid time-to-volume at advanced process nodes. In addition, Silicon Aware IP results in much higher test quality and reliability. Today, Virage Logic believes it is the only IP provider to offer Silicon Aware IP, an example of which is its Self-Test and Repair (STAR) Memory System™.

The conventional approach uses independently optimized Infrastructure IP and Physical IP, in which case the IP cannot work together in the most beneficial manner. This approach results in marginal yield improvements and long time-to-volume. As design complexities increase at the more advanced process nodes of 130nm and below, this approach becomes even less effective. What's more, because this approach is "bolt-on," it negatively impacts the System-on-Chip's (SoC's) area, speed and power.

Silicon Aware IP -- Video Tutorial by Dr. Yervant Zorian
Flash | Windows | Real

Learn how Virage Logic's Silicon Aware IP can help you maximize yield, lower test escapes, increase reliability and speed your time-to-volume. Listen to this short video tutorial by Virage Logic's Vice President and Chief Scientist, Dr. Yervant Zorian, recipient of the IEEE 2005 Industrial Pioneer Award.

Silicon Aware IP Brochure (PDF)
STAR Memory System
Agere Success Story (PDF)