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STAR™ Memory System
Virage Logic’s Self-Test and Repair (STAR) Memory System, first introduced in 2002, provides the most integrated cost-effective solution for embedding on-chip test and repair of memories in designs with a few to a few-thousand memory instances. Repairable or non-repairable embedded memories across any foundry or process node can be incorporated as part of the STAR Memory System to address a broad range of System-on-Chip (SoC) design requirements.
Already silicon proven in hundreds of designs on a variety of process nodes ranging from 180nm to 55nm, the STAR Memory System provides the most complete test solution to improve test quality, repair of manufacturing faults found in advanced processes and ease of integration into design.
The STAR Memory System provides a complete solution - allowing users to select and automatically integrate and verify all of the components required within the system. Specifically, the STAR Memory System consists of:
- Test and repair register transfer level (RTL) IP, such as STAR™ Processor, wrapper compiler, shared fuse processor, and synthesizable TAP controller
- Design automation tools such as STAR™ Builder for automated insertion of RTL and STAR™ Verifier for automated test bench generation
- Manufacturing automation tools such as STAR™ Vector Generator for automated generation of WGL/STIL and programmability in patterns, and STAR™ Silicon Debugger for rapid isolation, localization and classification of faults
- An open memory model for all memories. In order to generate STAR Memory System views, Virage Logic provides the MASIS memory description language. In addition a MASIS compiler is available to memory developers to automate generation and verification of the memory behavioral and structural description.
- Increased Profit Margin
The STAR Memory System can enable an increase of the native die yield through memory repair, leading to increased profit margins.
- Predictable High Quality with Substantial Reduction in Manufacturing Test Costs
High quality is achieved by tuning the test and repair engine to individual memory characteristics. The STAR Memory System uses advanced scrambling information to capture many new types of faults including challenging resistive, transition, and dynamic faults to meet today’s test escape level goals. This means that the possibility of test escapes is much lower with the STAR Memory System. By embedding the test and repair IP, STAR Memory System enables substantial reduction in manufacturing test costs through savings in tester time and external test development efforts.
- Shorter Time-to-Volume
The STAR Memory System has superior diagnostics capabilities to enable quick bring up of working silicon, thereby enabling manufacturing to quickly ramp to volume production. The STAR Memory System also has automated test bench capabilities and a proven validation flow to ensure a successful bring up of first silicon on the automatic test equipment.
- Minimum Impact on Design Characteristics (Performance, Power, and Area)
Because the test and repair system is transparently integrated within the STAR Memory System, it ensures minimal impact on timing and area and allows designers to quickly achieve timing closure. This advanced embedded test automation can reduce insertion time by weeks.
In order to provide STAR Memory System access to all memory developers, Virage Logic offers a proprietary memory description language called MASIS. The MASIS language, together with a MASIS compiler, simplifies and accelerates the process of creating and verifying memory views used by the STAR Memory System. By providing an open interface to the STAR Memory System, Virage Logic extends the value of the system to all users regardless of whether they elect to use Virage Logic memories, other commercially available third-party memories or internally developed memories. STAR Memory System users can enjoy the flexibility of being able to mix memories from various sources to meet their specific design requirements and still utilize the most advanced test and repair solution to develop higher quality end products.
Figure 1: The STAR Memory System’s open memory interface gives SoC designers the freedom to
use the system’s capabilities with their choice of Virage Logic memories, other commercially
available third-party memories or internally developed embedded memories.
To extend the value of the STAR Memory System to the test floor, Virage Logic offers an option called the STAR(tm) Yield Accelerator. The STAR Yield Accelerator addresses the requirement to rapidly, cost effectively and accurately identify, analyze, isolate and classify memory faults as designs are readied for transition from first silicon to volume manufacturing. The STAR Yield Accelerator consists of the, STAR(tm) Vector Generator and STAR(tm) Silicon Debugger, STAR(tm) Yield Analyzer, and STAR(tm) Silicon Browser components. Leveraging the infrastructure of the STAR Memory System, the STAR Yield Accelerator automatically generates vectors for test equipment and provides fault analysis and root-cause failure guidance based on silicon test results. Using STAR Yield Accelerator, test and product engineers can rapidly analyze failures manifested in embedded memories and inspect the physical location and class of each fault to determine the root cause without involving the IP vendor or SoC designer. The STAR Silicon Browser has advanced automation capabilities to interactively communicate with the STAR Memory System's infrastructure in a chip, through JTAG port for post silicon bring-up, system debug, diagnose, and characterization of embedded memories. The unique features of STAR Silicon Browser allow extraction of memory contents, multi-corner and multi-voltage characterization, precise physical failure localization, defect classification, and redundancy utilization analysis - all from an engineer's desktop, without utilizing expensive automatic test equipment.
Figure 2: The STAR Memory System, when used in conjunction with the STAR™ Yield Accelerator,
provides a complete RTL to test floor embedded memory test and repair solution that addresses
the needs of SoC designers, test and product engineers.
In summary, the STAR Memory System provides the most integrated cost-effective solution for embedding on-chip test and repair of memories in designs with a few to a few-thousand memory instances.
Manish Bhatia, Virage Logic Embedded Memory Test & Repair Product Marketing Manager
Avoiding Test Escapes to Achieve Near-Zero Defects Video Overview
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