May 2008

Welcome to the special May 2008 DAC issue of IP Times – your continuing source for semiconductor Intellectual Property (IP) news, trends, and developments from the semiconductor industry’s trusted IP partner. This is your opportunity to find out what exciting plans Virage Logic has on tap for the Design Automation Conference (DAC), being held in Anaheim, California, June 9-12, 2008.

Semiconductor IP Resource Center

Make an Informed Build or Buy Decision for Memory Controller Solutions – Chip Design Magazine
When planning a complex product-development project using an application-specific integrated circuit (ASIC) or system-on-a-chip (SoC), it’s critical to analyze the various risks, project costs, resources, and expertise required to allocate resources (money, equipment, and people). Read the article.

Virage Logic in the News

Virage Logic Speeds Time-to-Market with an All-Digital, High-Performance DDR2/3 PHY+DLL Solution
Virage Logic announced its Intelli™ DDR2/3 PHY+DLL all-digital PHY+DLL high-performance DDR solution. Supporting speeds of up to 1066 Mbps in 65-nanometer (nm) G processes, the all-digital Intelli DDR2/3 PHY+DLL achieves performance and resolution levels that were previously only possible with analog solutions. Read the announcement.

Virage Logic Embedded Multi-Time Programmable Non-Volatile Memory Gains Acceptance in Military Applications
Virage Logic recently announced that its NOVeA® 3.0 embedded multi-time programmable (MTP) non-volatile memory (NVM) product has been selected for use in multiple military temperature range applications. First introduced in 2002, NOVeA has steadily expanded its popularity for use in high volume consumer and industrial applications, and is now gaining acceptance in the security and defense communities. Read more.

Virage Logic’s High-Efficiency DDR Memory Controller Selected by Server Virtualization Solutions Leader 3Leaf Systems
3Leaf Systems, a provider of next-generation server virtualization solutions for enterprise data centers, recently selected Virage Logic’s all-digital Intelli™ Double Data Rate (DDR) Memory Controller interface solution that allowed them to reach performance levels typically only achieved by mainframes. Learn more.

CSR Selects Virage Logic as Its Trusted IP Partner for Next-Generation Bluetooth® Devices
CSR of Cambridge, United Kingdom, a top global supplier of single chip wireless communications products, has licensed Virage Logic's IP to enable its next-generation technology. CSR will use Virage Logic's Area, Speed and Power (ASAP™) Memory, Self-Test and Repair (STAR™) Memory and STAR™ Yield Accelerator products for design of its BlueCore™.  Read the announcement.

Virage Logic’s DDR Memory Controller Interface Provides High Performance Data Transfer at Higher Efficiency and Lower Power
Virage Logic recently announced that its Intelli™ Double Data Rate (DDR) memory controller interface can provide up to a 20 percent efficiency gain for high-performance applications, while still maintaining low-power. Architected from the ground up to provide a combination of low-latency, high-performance and low-power options, the Intelli DDR solution incorporates intelligent scheduling algorithms for superior system bandwidth. Learn more.

Proceed with Confidence to Booth # 1324 at DAC…
Climb the Rockwall.

June 9-12, 2008
45th Design Automation Conference
Anaheim Convention Center

Advanced IP Technology.  Low-Power Management Solutions for 65nm and 40nm.  DDR 1/2/3 Memory Interface IP Solutions. Embedded Test and Repair for Increased Yield and Manufacturability at Advanced Processes.  Embedded NVM Flash on a Standard CMOS process.

Visit Virage Logic at DAC to learn how you can accelerate your silicon success with advanced
IP for 65nm and 45nm designs. Meet with the semiconductor industry’s trusted IP partner to learn more about our silicon proven solutions for embedded memories, logic libraries, DDR memory controllers, non-volatile memories, and I/Os. As an integral part of the SoC design ecosystem, find out how Virage Logic's collaborative foundry and technology partner relationships and flexible business models can help accelerate your silicon success.

Accelerate Your Silicon Success – Request A Meeting Now!

Virage Logic Meetings

• SiWare™ Memory & SiWare™ Logic Low-Power Management Solutions
  for Advanced Technology Nodes
• NOVeA® - Embedded Flash on Standard CMOS Process for Secure Military,
  Encryption, Digital Rights Management, RFID & Code Storage Applications
• Intelli™ DDR Memory Controllers –- DRAM Interface IP Optimized for High-Efficiency
  in All Market Segments
• STAR™ Memory System Combines Soft IP Test & Repair, EDA & Manufacturing Tools
  for RTL to Yield Ramp Up
• Foundry Partner Collaboration & Business Model Options for Accelerating Silicon Success
  at Advanced Processes

Virage Logic DAC Events

SUNDAY, June 8, 4:30 PM - 7:30 PM | Pacific Ballroom
EDAC Reception Sponsor: Let's Make a Profit
MONDAY June 09, 2008, 9:00 AM - 1:45 PM | Room 205A
Workshop: Women in Design Automation: Networking, Negotiation, and Nonsense:
Achieving Career Balance in an Unbalanced World
MONDAY June 09, 2008, 1:00 PM - 1:55 PM | IP Talks! Booth #2358
Presentation: Virage Logic Corporate Overview – The Industry’s Trusted IP Partner
MONDAY June 09, 2008, 2:00 PM - 5:00 PM | Room 213D – Hosted By Apache Design
Hands-On Tutorial: IP Validation for Macro and Embedded SoC
MONDAY June 09, 2008, 3:30 PM - 3:50 PM | TSMC Booth #2341
Presentation: Virage Logic Corporate Overview – The Industry’s Trusted IP Partner
TUESDAY June 10, 2008, 9:30 AM – 9:50 AM | TSMC Booth #2341
Presentation: Virage Logic Corporate Overview – The Industry’s Trusted IP Partner
TUESDAY June 10, 2008, 10:30 AM - 6:00 PM | Room 207D
Management Day at 45th Design Automation Conference
TUESDAY June 10, 2008, 10:30 AM - 11:15 AM | DAC Pavilion Booth #364
Pavilion Panel:45nm: Collaborate, Aggregate, Differentiate
WEDNESDAY June 11, 2008, 8:00 AM - 11:00 AM | Room 213D – Hosted By Virage Logic
Hands-On Tutorial: Integration, Test, Repair and Debug of Embedded Memory IP in an SoC
WEDNESDAY June 11, 2008, 9:00 AM, 1:30 PM, 4:00 PM | UMC Booth #2306
Presentation: Virage Logic Corporate Overview – The Industry’s Trusted IP Partner
WEDNESDAY June 11, 2008, 1:00 PM - 2:00 PM | DAC Pavilion Booth #364
Pavilion Panel: Advanced Low Power Techniques: Is Your Design Method Too Powerful?
WEDNESDAY June 11, 2008, 1:30 PM - 1:50 PM | TSMC Booth #2341
Presentation: Virage Logic Corporate Overview – The Industry’s Trusted IP Partner
WEDNESDAY June 11, 2008, 3:45 PM | Common Platform Booth #628
Presentation: Virage Logic Corporate Overview – The Industry’s Trusted IP Partner
THURSDAY June 12, 2008, 10:00 AM - 10:45 AM | DAC Pavilion Booth #364
Pavilion Panel: Negotiating a Successful Career

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