June-July 2008

Welcome to the June-July 2008 issue of IP Times – your continuing source for semiconductor Intellectual Property (IP) news, trends, and developments. Virage Logic has been very active with news and product announcements in the last few weeks, so this is your opportunity to get up to speed with the industry’s trusted semiconductor IP partner.

Resource Center

EuroAsia IC Industry Awards 2008 – Cast Your Vote Now for Virage Logic!
As tool and service providers become technology partners, and research and development is now a collaborative effort, close relationships between IP providers and customers are more important than ever.

As the industry’s trusted semiconductor IP partner, Virage Logic is proud to announce its nomination in the Yield Management – Best Process Award category of the EuroAsia IC Industry Awards for it’s Self-Test and Repair (STAR™) Yield Accelerator. Users determine who will win based on the number of votes.

Offering capabilities far beyond conventional physical de-processing and manual analysis, Virage Logic’s STAR Yield Accelerator can pinpoint the exact physical location of memory faults and provide guidance of the root cause. By enabling engineers to troubleshoot yield issues in a secure and efficient manner, the STAR Yield Accelerator protects both manufacturers’ sensitive process data and designers’ closely guarded design data.

This is your opportunity to let the industry know you think Virage Logic’s STAR Yield Accelerator is an industry-leading embedded test and repair solution. VOTE NOW!

Register Now! STAR™ Memory System Class – August 12-13, 2008
It’s not too late to register for this extensive two-day course featuring lectures, hands-on tutorials, and labs to help you learn how to integrate the STAR Memory System into your SoC designs and accelerate your silicon success. STAR Memory System customers have enjoyed improved yields by up to 250%, so don’t miss this opportunity to learn how you can effectively implement this solution to help increase your yields. Seating is limited.  Register Now.

Virage Logic in the News

Virage Logic Acquires Impinj's Logic Non-Volatile Memory (NVM) IP Business
Virage Logic recently announced the acquisition of Impinj's logic non-volatile memory (NVM) IP business. The purchase extends Virage Logic's embedded memory leadership position into the rapidly growing NVM market for standard CMOS processes. The strong logic NVM IP product portfolio from Impinj provides the perfect complement to Virage Logic’s existing NVM product offering. Read more.

Virage Logic Expands Memory Interface Product Portfolio With New DDR3 Solution That Supports Speeds Up to 1.6 Gb/s
With the recent introduction of the Intelli™ DDR3 memory interface solution, Virage Logic has extended its leadership to provide advanced technology solutions beyond the chip level to address the system-level impact on high-speed IP interfaces, such as DDR interfaces. Building on its Silicon Aware IP™ offering that addresses the impact of advanced process behavior on System-on-Chip (SoC) devices, the new Intelli DDR3 System Aware IP™ offering is capable of managing the impact of the environment – SoC core to interface, interface to package, package to board – on the system behavior and performance. System Aware IP is built for signal integrity awareness, yet meets the functional as well as, performance, power, and area requirements. Learn more.

Virage Logic Unveils One Mega-Bit Embedded Reprogrammable Non-Volatile Memory (NVM) on Standard CMOS Process
The recent announcement of Virage Logic’s emPROM™ Memory System, introduces a new family of embedded multi-time programmable (MTP) NVM for flexible program code storage in SoC devices. Combining user-defined functionality with Virage Logic's high-capacity read-only memory (ROM) and NOVeA® Flash memory, emPROM provides secure, fully integrated embedded NVM for SoC designs requiring up to 16 Megabits of code storage and is manufactured on industry standard CMOS processes with no additional mask or process steps. Read more.

Virage Logic Supports TSMC's Power Trim Service™ for Advanced Process Nodes
Virage Logic recently announced that it is the first IP provider to support TSMC's Power Trim Service. Through TSMC’s Power Trim Service, Virage Logic’s power trim compliant libraries enable SoC designers to reduce leakage power without sacrificing area. Lean more.

Virage Logic Delivers Open RTL to Test Floor Embedded Memory Test and Repair Subsystem
At the recent Design Automation Conference (DAC) in Anaheim, Virage Logic showcased a new release of the STAR™ Memory System that features an open memory interface, giving SoC designers the freedom to use the system's capabilities with their choice of Virage Logic memories, other commercially available third-party memories, or with internally developed embedded memories. The STAR Memory System, when used in conjunction with the STAR Yield Accelerator provides a complete RTL to test floor embedded memory test and repair solution that addresses the needs of SoC designers, test and product engineers. Read more.

Upcoming Events

Flash Memory Summit
Wednesday, August 13, 2008 – Open Session 101: Design Methods (2:40pm-3:45pm)
Santa Clara Marriott Hotel, Santa Clara, CA
Flash memory is a key technology enabling new designs for products in the consumer, computer, and enterprise markets, and the Flash Memory Summit is where you can hear directly from the people and companies that are making these products happen.With many opportunities for you to ask questions, you won’t want to miss this session to hear Virage Logic present a paper on “Embedded Non-Volatile Memory on a Standard CMOS Logic Process” at the Flash Memory Summit. Register now.

CDNLive! 2008 Silicon Valley
September 9-11, 2008
San Jose Marriott Hotel and San Jose McEnery Convention Center, San Jose, CA
CDNLive! attendees will learn how to overcome complex design issues and discover the latest technology solutions to address their design challenges. As a Cadence partner, Virage Logic’s IP experts will be on hand with important information about how we work in collaboration to provide the best IP solutions for your design requirements. Early Bird Registration.

Synopsys Users Group (SNUG) Boston
September 22-23, 2008  
Boston Marriott Newton Hotel, Newton, MA
Plan to attend SNUG in Boston and be sure to stop by Virage Logic’s Gold Sponsor booth at the Interoperability Fair to meet with the industry’s foremost IP experts to learn more about the company’s broad portfolio of silicon proven semiconductor IP. Register Now.

Global Semiconductor Association (GSA) IP Conference
September 24-25, 2008
Santa Clara Convention Center, Santa Clara, CA
This inaugural event will address the business, quality and metric issues surrounding quality IP and how important it is for semiconductor suppliers to incorporate a healthy IP ecosystem within their business strategy. Showcasing perspectives from design, third-party IP vendors, foundry, and EDA companies, topics will concentrate on the opportunities, risks and rewards in obtaining quality IP. Don’t miss the opportunity to hear Virage Logic’s IP experts who will be participating on several panels at this event. Register now.

Virage Logic Membership Has its Access Privileges

Become a Virage Logic Member for exclusive access to Foundry Sponsored front-end design kits, application notes, silicon characterization reports, white papers, and much more! It’s easy and only takes a few minutes to become a Virage Logic Member. Sign up today and begin enjoying the benefits of Virage Logic Membership.

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