April 2008

Welcome to the April 2008 issue of IP Times – your continuing source for semiconductor Intellectual Property (IP) news, trends, and developments from the semiconductor industry’s trusted IP partner.

Semiconductor IP Resource Center

Hurry to Register – STAR^TM Memory System Class – May 13-14, 2008
Please note the new dates for the upcoming STAR Memory System class! This extensive two-day course features lectures, hands-on tutorials, and labs to help you learn how to integrate the STAR Memory System into your designs and accelerate your silicon success. STAR Memory System customers have improved yields by up to 250%, so don’t miss this opportunity to learn how you can effectively implement this solution to increase your yields.  Register Now.

Virage Logic in the News

Virage Logic Appoints Dr. Alex Shubat to Newly Created Position of Chief Operating Officer
Virage Logic recently announced the appointment of Dr. Alex Shubat to the newly created position of chief operating officer (COO). Dr. Shubat, one of Virage Logic's co-founders, previously served as the company's chief technical officer (CTO). Dr. Shubat's expanded role will enable him to help drive the next phase of the company's growth. Read the announcement.

Virage Logic Strengthens Low Power IP Product Portfolio with Availability of 65nm CPF-Enabled Ultra-Low-Power Standard Cell Libraries
Virage Logic recently announced the availability of its Common Power Format (CPF) enabled 65-nanometer (nm) Standard Cell logic libraries. Virage Logic's 65nm Ultra-Low-Power (ULP) product offering helps manage low-power designs targeting applications in the rapidly expanding mobile consumer market that require advanced power reduction techniques such as power shut-down, state retention and multiple voltage islands. Read more.

Virage Logic First to Deliver Complete Memory Compiler and Logic Library IP Portfolio for TSMC’s 40nm Process
Virage Logic announced the availability of its memory compilers and logic libraries for the TSMC 40-nm process. The company’s 40nm SiWare^TM product portfolio provides semiconductor companies with physical IP that is designed to enable System-on-Chips (SoCs) to run faster, manage power more efficiently, use less area, and achieve higher manufacturing yields.  Read more.

Virage Logic's DDR Memory Controller Interface Provides High-Performance Data Transfer at Higher Efficiency and Lower Power
Virage Logic recently announced that its Intelli^TM Double Data Rate  (DDR) memory controller interface can provide up to a 20 percent  efficiency gain for high-performance applications, while still maintaining low-power. Architected from the ground up to provide a combination of low-latency, high-performance and low-power options, the Intelli DDR solution delivers intelligent scheduling algorithms for superior system bandwidth. Read more.

Upcoming Industry Events

As the semiconductor industry’s trusted IP partner, Virage Logic participates in a variety of global industry events to help educate the SoC design community on the latest advanced IP technology. See below for a list of upcoming events where you can hear Virage Logic’s IP experts address the complex issues facing the industry today. 

IEEE VTS’08
April 28-30, 2008
Rancho Bernardo Inn, San Diego, California
Don’t miss the upcoming VTS’08 conference where Dr. Yervant Zorian, Virage Logic’s Vice President and Chief Scientist, will be featured on the “Design for Yield and Manufacturability” IP panel session. He will also be moderating the “Mitigating Reliability, Yield and Power Issues in Nano-CMOS: Design Problem or EDA Problem?” panel that is being co-hosted by Design & Test magazine. Virage Logic will also be presenting the technical paper, “An Efficient March-Based Three-Phase Fault Location and Full Diagnosis Algorithm for Realistic Two-Operation Dynamic Faults in Random Access Memories,” and participating as the organizer for several other technical sessions at this event. Register to attend.

Upcoming VIP Partner Events

Virage Logic’s VIP Partner Program brings together technology and business alliances with our industry partners for the benefit of our mutual customers. As part of the VIP Partner Program, Virage Logic supports our partners’ global events, such as the ones listed below.

TSMC North America Technology Symposiums
April 22, 2008 – San Jose
April 25, 2008 – Boston (Waltham), MA
April 28, 2008 – Austin, TX
The annual TSMC Technology Symposiums will offer news and insights on advanced technologies; providing programs and sessions to help keep you informed. As TSMC’s early development partner, be sure to visit the Virage Logic booth at all three locations to learn how TSMC and Virage Logic partner to provide mutual customers with integrated IP solutions for advanced technology nodes. Register Now.

CDNLive! EMEA 2008 - April 28-30, 2008
Hilton Munich Park, Munich, Germany
The CDNLive! attendees will learn how to overcome complex design issues and discover the latest technology solutions to address their design challenges. As Cadence’s partner, Virage Logic IP experts will be on hand with important information about how we work in collaboration to provide the best design solutions for your requirement challenges. Register Now.

MIPS Technical Seminar
April 29, 2008
Daniel Hotel, Herzelia, Israel
Join Virage Logic at this unique one-day seminar hosted by MIPS Technologies. This is your chance to learn more about Virage Logic’s silicon proven advanced IP technology and how we work together as ecosystem partners with MIPS to benefit our mutual customers. Register to attend.

Virage Logic Membership Has its Access Privileges

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