Partner Profile: Open-Silicon and Virage Logic Team to Deliver Silicon Proven Low Power SoC Designs

As more and more designers develop energy efficient devices, combining low power IP with low power design technology enables the development of silicon that is significantly more energy efficient. In February, Open-Silicon, Inc., a leading ASIC design and semiconductor manufacturing company, and Virage Logic announced an alliance to provide just such a solution.

The advanced power management features within the Virage Logic SiWare™ Memory compilers and SiWare™ Logic libraries enable designers to dramatically reduce leakage current while maximizing performance. Open-Silicon’s VariMAX back biasing technology similarly works with Virage Logic’s SiWare Logic standard cell libraries to reduce leakage for the IC’s logic.

Changing the amount of bias on individual chips, VariMAX tunes the silicon for optimum power and thereby boosts production yields. This latest collaboration builds on a recentl co-developed test chip with working silicon running at 1.1GHz that was achieved using Open-Silicon’s patented CoreMAX™ performance enhancement technology and Virage Logic’s advanced SiWare Memory compilers.

CoreMAX techniques include design Boolean analysis, static timing, cell placement, route estimation and simultaneous optimization at the logical, physical and transistor levels. Based on the needs of each critical path in the design, CoreMAX may change cells, move cells, or even create new cells on-the-fly, performing a library-compatible layout for each new cell and characterizing them for use throughout the EDA environment. These new cells offer unique drive strengths and functionality that enable maximum device performance.

Virage Logic’s SiWare High-Density memory compilers are optimized to generate memories with the absolute minimum area. Compile-time options for process threshold variants, power saving modes, read and write margin extensions,

ultra-low voltage operation, and innovative design for at-speed test enable SoC designers to configure optimal solutions for their specific design requirements.

"As power management and efficiency are becoming increasingly critical in a multiplicity of products and technologies, our collaboration with Open-Silicon underscores how we are working with our design ecosystem partners to help SoC designers address these challenges,”

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